The behavior of a circuit under test is often modified to increase the level of activity of all its components to facilitate testing of the circuit. However, the reconfigured circuit might consume an average amount of power that is significantly higher from that measured during normal operation for the same clock frequency. This is especially true when the circuit is tested at high-speed to detect defects that might cause delay faults, for example. Excessive power consumption due to the increased circuit activity (or toggle rate) can damage the circuit itself or the test equipment and it can also invalidate the results of the test.
The additional stress caused by a controlled amount of additional power consumption can, however, be used to evaluate the reliability of the circuit. It allows the temperature of the circuit to be increased without requiring additional equipment (e.g. hot chuck, furnace). The elevated temperature is known to reduce the performance of a circuit. This kind of test is used to screen circuits that must be able to function at high temperature.
Jaber et al U.S. Pat. No. 5,614,838 discloses a reduced power apparatus and method for testing high speed components. The method is only applicable to a specific type of circuit known as Level-Sensitive Scan Design (LSSD), where separate clock sources are needed to control the circuit in normal and test modes of operation. Even though the patentee claims that the method is applicable to other types circuits, it is neither obvious nor practical to use the method for circuits other than LSSD circuits. In general, only one clock is available for controlling normal and test modes of operation (e.g. multiplexed scan). Therefore, it is not possible to gate the clock during the shift operations. Also, the method does not allow adjustment of the level of power consumption, which might invalidate the performance test results.